Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0 . 18 μ m CMOS process

Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC) by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ)-comparator, the encoder and the parallel input serial output (PISO) register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 μm and the power dissipation is 0.162 μW with 1.6 V supply voltage.


Introduction
Technological developments and use of wirelesssystem applications with low power consumption have become one of the main attractions in circuit design.Explosive growth of embedded sensor into radio frequency identification (RFID) tag is nowadays used with low voltage supply.Sensor data, integrated into the RFID systems, require ADC circuits.The ADC design presented in this paper is a converter suitable for a temperature sensor.The temperature sensor is implanted on the RFID-Tag chip, which is integrated into the RFID or wireless system.The design is expected to have lower power dissipation and operating voltage, small area size and easy to integrate with the other circuits.The ADC which is in accordance with that purpose is a Flash-ADC by TIQ-Comparator application.The Flash-ADC has many advantages, such as high speed, high linearity, low voltage and reduced power dissipation (YOO et al., 2003).Previous researches have undertaken a variety of methods to get the best performance of ADC, as Table 1 shows.
Table 1 shows that previous research generally developed design flash ADC with the lowest power  CHANDRAKASAN, 2009).Further, (WU et al., 2012) proposed the SAR ADC design method with a power dissipation of 1200 μW and (SAHOO; RAZAVI, 2009) proposed a method pipeline ADC with 348 mW power dissipation, but they did not get a lower power consumption compared to the flash ADC.Current research proposed a low power dissipation flash ADC design with TIQ-comparator, encoder and PISO register development to obtain the best performance which is compatible for use with the temperature sensor system.

Material and methods
The complete system of flash ADC consists of three main blocks, or rather, TIQ comparator, encoder and PISO registers, as shown in Figure 1.The TIQ-Comparator is functioning as data quantization of the analog data to thermometer code (TC), and is important for linearity and accuracy of the data transfer.The encoder makes sharper thresholding of comparator output and provides full digital output voltage swing and converting to 6-bit binary code.The PISO register works to process 6bit of parallel to serial data.
The temperature sensor will use this design at a range between -100 and 200°C.The sensor has a range analog output from 285 to 560 mV with the supply voltage 1.6 V and 31.14 μW power consumption.This sensor was developed on our previous research and match to input of flash ADC propose.
A basic TIQ Comparator circuit consists of two cascaded CMOS inverters, as shown Figure 2 (YOO et al., 2003).The first inverter works as voltage reference to the ADC system.The second inverter works as the gain booster to keep linearity in balance from the voltage rising and falling intervals (YOO et al., 2003).In previous researches several methods for design of TIQ-comparator have been studied, such as: the analog input signal quantization level is set in the first stage by changing the voltage transfer curve (VTC) by transistor sizing (TANGEL; CHOY, 2004) and (SUDAKAR et al., 2011), the size of both transistor channel lengths, L and width, W are adjusted (YOO et al., 2003), third, by only adjusting W and L is fixed (TANGEL; CHOY, 2004).
Current research applies to another method by adjusting L and keeping W fixed.The advantages of this method are reduced power consumption and area of the layout.Increasing L reduces the transistor drain current, I D according to (UYEMURA, 1988) for a transistor in saturated condition as: where:    In this calculation, the size of the channel L for the TIQ-comparator No. 1 to 21 only is obtained, with channel L from 0.51 μm to 2.91 μm, as shown in Figure 4.

In t for NM equatio
For the next comparator No. 22 to 64 one or two PMOS transistors are inserted as compensation in diode connection to complement the achievement of the expected voltage input range to the lower side.The compensation transistor is inserted between VDD to the first inverter PMOS transistors, as shown in Figure 5.Meanwhile, the design size of the L and channel W of the second inverter are fixed, according to the design standard of the 0.18 -μm CMOS Technology.The standard design is 0.18 μm of L and 1.4 μm of W for PMOS and NMOS transistors respectively.
In previous researches, there are many methods for the design of the encoder circuit.There are; Fat-tree encoder (RAJESWARI et al., 2012); MUX-based encoder (ARUNKUMAR et al., 2012) and (SANDNER et al., 2005); bubble error correction (BEC) circuit; ROM-based encoder (KULKARNI et al., 2010); logic-based encoder (KUMAR; KOLHE, 2011).All the methods propose the same advantages such as high speed, high resolution, low power and etc. Logic-based encoder is the best performance and matches the proposed design.Due in this design, there are two main points that are low power and simple circuit.For the benefits of low power and simple circuit, the encoder is implementing the circuits by using CMOS logic gates in CEDEC standard library.In this process, the encoder has two functions that are used to eliminate the bubbleerror and convert 64-level thermometer code into 6-bit binary code.The bubble error is the result of many sources, for instance, clock jitter, device mismatch, offset voltage.The input thermometer code of a circuit is invalid code and there is no correction circuit; consequently output of the ADC in this case is incorrect.
where, T is a thermometer code in which T64 is LSB and T1 is MSB.
G is a gray code, in which G0 is LSB and G5 is MSB.In the following expressions b is the binary code where b0 is LSB and b5 is MSB.Table 3. Thermometer code to gray code and to 6-bit code. No.

Results and Discussion
The circuit design is designed and simulated by using the tools of the Mentor Graphics Design Architect (DA) CEDEC_KIT.The design and simulations are carried out to achieve repeatedly a linear quantization value.To obtain a linear quantization value in the simulation of 0.0 V to 0.61 V, it is given by the DC input signal, as in Figure 9, while to obtain a frequency response of quantization from 1 to 10 KHz, it is given by the AC signal input, shown by Figure 10. Figure 9 shows the conversion of analog input to quantization output responding range between 0.285 V and 0. 6 V.During the increment of 5 mV in the DC input, the quantization output increases 1 level.These phenomena are convincing to quantify the analog data temperature sensor with range between 0.36 and 0.56V only.Table 5 shows the comparative results of proposed ADC with the other flash ADC architectures.It may be noted that the proposed design has the lowest power dissipation which emphasizes an innovative challenge.The layout area design was shown in Figure 14 with the pad terminal included, whereas the other designs are featured by excluding pad terminal.However, this layout size of the pad depends on the library CEDEC standard design.Hence, the proposed design did not appear in the smallest layout size in Table 5.

Conclusion
The flash ADC is designed and verified by using the Mentor Graphics VLSI Design Software.The final chip is designed by CEDEC Industry Standard I/O Cell Library for Fabrication Lab Silterra Malaysia.It consists of 64 pairs of CMOS inverters in the-TIQ comparator part, the logic based is used for the encoder part, and D-type flip-flop for the PISO register develop.The design has an input range of 285 to 600 mV and 6-bit resolution output.The chip area of the designed ADC is 844.48 x 764.77 μm 2 .The power dissipation is 0.162 μW in 1.6 V supply voltage and the sinusoidal input voltage of 0V to 0.6 V-peak at the 10 KHz frequency and positive half wave transition condition.The design is suitable for use to the wireless temperature sensor system.

Figure 1 .
Figure 1.Block diagram of the flash ADC.

Figure 9 .
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Figure 15.The

Table 1 .
Comparison of results of ADCs design.

Table 4 .
Parallel 6-bit binary to serial on 1 byte data.

Table 5 .
Comparison of the propose design with other flash ADCs.